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<title>MTB CAT1 Peripheral driver library: SysClk       (System Clock)</title>
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<div class="header">
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<a href="#groups">API Reference</a>  </div>
  <div class="headertitle">
<div class="title">SysClk (System Clock)</div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>The System Clock (SysClk) driver contains the API for configuring system and peripheral clocks. </p>
<p>The functions and other declarations used in this driver are in cy_sysclk.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.</p>
<p>Firmware uses the API to configure, enable, or disable a clock.</p>
<p>The clock system includes a variety of resources that can vary per device, including:</p><ul>
<li>Internal clock sources such as internal oscillators</li>
<li>External clock sources such as crystal oscillators or a signal on an I/O pin</li>
<li>Generated clocks such as an FLL, a PLL, and peripheral clocks</li>
</ul>
<p>Consult the Technical Reference Manual for your device for details of the clock system.</p>
<p>The PDL defines clock system capabilities in:<br />
devices/COMPONENT_CAT1&lt;subcategory&gt;/include/&lt;series&gt;_config.h. (E.g. devices/COMPONENT_CAT1A/include/psoc6_01_config.h).</p>
<p>As an illustration of the clocking system, the following diagram shows the PSoC 63 series clock tree. The actual tree may vary depending on the device series. Consult the Technical Reference Manual for your device for details. </p><div class="image">
<img src="sysclk_tree.png" alt="sysclk_tree.png"/>
</div>
<p>The sysclk driver supports multiple peripheral clocks, as well as the fast clock, slow clock, backup domain clock, timer clock, and pump clock. The API for any given clock contains the functions to manage that clock. Functions for clock measurement and trimming are also provided.</p>
<h1><a class="anchor" id="group_sysclk_configuration"></a>
Configuration Considerations</h1>
<p>The availability of clock functions depend on the availability of the chip resources that support those functions. Consult the device TRM before attempting to use these functions. For PSoC 64 devices the clocks configurations are restricted and limited. Refer to the PRA driver, and the TRM and datasheet for details.</p>
<dl class="section warning"><dt>Warning</dt><dd>On the diagram above, the yellow muxes are glitch-safe. All glitch-safe mux transitions take four cycles of the source clock. It is not allowed to turn off the source clock during that time.</dd></dl>
<p>PSoC 6 power modes limit the maximum clock frequency. Refer to the SysPm driver and the TRM for details.</p>
<h1><a class="anchor" id="group_sysclk_more_information"></a>
More Information</h1>
<p>Refer to the technical reference manual (TRM) and the device datasheet.</p>
<h1><a class="anchor" id="group_sysclk_changelog"></a>
Changelog</h1>
<table class="doxtable">
<tr>
<th>Version</th><th>Changes</th><th>Reason for Change </th></tr>
<tr>
<td>3.140 </td><td>Update PLL configuration for CAT1D devices. </td><td></td></tr>
<tr>
<td>3.130 </td><td>Corrects fractional enable behavior in <a class="el" href="group__group__sysclk__pll__funcs.html#gad498857f6d3c3b8df8dd176391d07f6f">Cy_SysClk_Pll400MConfigure</a>. Only enables fractional divider if the fractional divider is non-zero.  </td></tr>
<tr>
<td>3.120 </td><td>Added PSOC C3 device support. </td><td>New devices support added.  </td></tr>
<tr>
<td>3.110 </td><td>Added support for LPECO feature.<br />
Newly added APIs: <br />
 <a class="el" href="group__group__sysclk__lpeco__funcs.html#ga0133fbf2478170b6f4db1b51056686a0" title="Configures the low-power external crystal oscillator based on crystal characteristics. ">Cy_SysClk_LpEcoConfigure()</a> <br />
 <a class="el" href="group__group__sysclk__lpeco__funcs.html#ga582a1f2f3058d56a4df2954372639722" title="Enables the low-power external crystal oscillator (LPECO). ">Cy_SysClk_LpEcoEnable()</a> <br />
 <a class="el" href="group__group__sysclk__lpeco__funcs.html#ga9c4405715f1b13bd53ca0cb180260a9e" title="Disables the low-power external crystal oscillator (LPECO). ">Cy_SysClk_LpEcoDisable()</a> <br />
 <a class="el" href="group__group__sysclk__lpeco__funcs.html#ga24da962a1d4207bb8edd705f05385a43" title="Stores the low-power external crystal oscillator (LPECO) frequency in a global variable within Sysclk...">Cy_SysClk_LpEcoSetFrequency()</a> <br />
 <a class="el" href="group__group__sysclk__lpeco__funcs.html#gab4e4a9a167535a83e596db0bb7d4d7d8" title="Returns the frequency of the low-power external crystal oscillator (LPECO). ">Cy_SysClk_LpEcoGetFrequency()</a> <br />
 <a class="el" href="group__group__sysclk__lpeco__funcs.html#ga53ba03d3db8acd0af60ab05cec83f115" title="Configures the low-power external crystal oscillator (LPECO) Prescaler and derives clk_lpeco_prescale...">Cy_SysClk_LpEcoPrescaleConfigure()</a> <br />
 <a class="el" href="group__group__sysclk__lpeco__funcs.html#ga5960c34135fa51a719e693020aa6887a" title="Reports whether or not LPECO Prescale is enabled. ">Cy_SysClk_LpEcoPrescaleIsEnabled()</a> <br />
 <a class="el" href="group__group__sysclk__lpeco__funcs.html#gaf2206a208d012f6b41a0c223d33d52ce" title="Reports the current status of the low-power external crystal oscillator (LPECO) amplitude detection...">Cy_SysClk_LpEcoAmplitudeOkay()</a> <br />
 <a class="el" href="group__group__sysclk__lpeco__funcs.html#gacb04faf587999a58e7785a3f53bea60b" title="Indicates whether or not the low-power external crystal oscillator (LPECO) has had enough time to sta...">Cy_SysClk_LpEcoIsReady()</a>   </td></tr>
<tr>
<td>3.100 </td><td>Added support for CSV feature and fixed coverity bugs. </td><td>Added CSV feature support for CAT1D and bug fixes.  </td></tr>
<tr>
<td>3.90 </td><td>Added support for TRAVEO&trade; II Body Entry devices.<br />
 Pre-processor check for MXS40SRSS version now groups ver. 2 with ver. 3. Previously ver. 2 was grouped with ver. 1.<br />
 In cy_sysclk_v2 source, added pre-processor logic to include/exclude certain SRSS versions.<br />
 Renamed PERI_DIV Defines to PERI_PCLK_GR_DIV for CAT1B and CAT1C. Changed pre-processor logic and set initial values to 0 for grpNum, instNum, locFrac, and locDiv variables to prevent uninitialized value access. Added pre-processor logic to prevent use of PLL400M API for non-compatible devices. Added "Unsupported Core Type" warning messages. In cy_sysclk_v2 source, added API <a class="el" href="group__group__sysclk__clk__fast__funcs.html#ga414d0aa5c8df4a5b16c91614ff967e3a">Cy_SysClk_ClkFastGetDivider</a>. </td><td>Code enhancement and support for new devices.  </td></tr>
<tr>
<td>3.80 </td><td>Added <a class="el" href="group__group__sysclk__pilo__funcs.html#ga3a27da8dadb92695750b12f41c91be06">Cy_SysClk_PiloOkay</a> new API and few macros. Updated <a class="el" href="group__group__sysclk__pilo__funcs.html#ga92e44b1390d7cabf2c597c45a5fdd309">Cy_SysClk_PiloEnable</a>. </td><td>Usability enhancement.  </td></tr>
<tr>
<td>3.70 </td><td>Added new APIs <a class="el" href="group__group__sysclk__clk__pwr__funcs.html#ga67797f8c99ea82f42ee9c851c0c320cf">Cy_SysClk_ClkPwrSetDivider</a>, <a class="el" href="group__group__sysclk__clk__pwr__funcs.html#ga1e5eb62dc8e5d6e2868ad6e9ab4e10da">Cy_SysClk_ClkPwrGetDivider</a>, <a class="el" href="group__group__sysclk__clk__pwr__funcs.html#ga9c2e470db36c5e854811d539035d0ad0">Cy_SysClk_ClkPwrGetFrequency</a>, <a class="el" href="group__group__sysclk__clk__pwr__funcs.html#ga56d3459b796e0c51e85da74ba368eab7">Cy_SysClk_ClkPwrSetSource</a>, <a class="el" href="group__group__sysclk__clk__pwr__funcs.html#ga35a0804ce9e5014d36a0fdfe6edd0db2">Cy_SysClk_ClkPwrGetSource</a>. <br />
 and enum <a class="el" href="group__group__sysclk__clk__pwr__enums.html#gaea34f48dfb3fbef4d7ff33862cbd2f0a">cy_en_clkpwr_in_sources_t</a>  </td><td>Support Added for future devices of the CAT1B.  </td></tr>
<tr>
<td rowspan="2">3.60 </td><td>Support for CAT1D devices is added </td><td>New devices support added  </td></tr>
<tr>
<td>Remove local structure initialization to avoid optimization </td><td>Code cleanup  </td></tr>
<tr>
<td>3.50 </td><td>Bug fixes and few new APIs addition.<br />
Newly added APIs: <br />
 <a class="el" href="group__group__sysclk__pll__funcs.html#ga219fd6d8d1d18090fe6d7002610ac021" title="Returns the output frequency of the PLL. ">Cy_SysClk_PllGetFrequency()</a> for CAT1A,CAT1C and CAT1D devices, <br />
 <a class="el" href="group__group__sysclk__pll__funcs.html#gabdf2396edece2bf47abd72603fc791e5" title="Gets the frequency of PLL200M. ">Cy_SysClk_Pll200MGetFrequency()</a> for CAT1C devices, <br />
 <a class="el" href="group__group__sysclk__pll__funcs.html#ga1e83e55b944bb47222d309ede5569d38" title="Gets the frequency of PLL400M. ">Cy_SysClk_Pll400MGetFrequency()</a> for CAT1C devices, <br />
 <a class="el" href="group__group__sysclk__imo__funcs.html#ga40861bc2380f871a06ef0600ccbd4dd5" title="Enables the IMO. ">Cy_SysClk_ImoEnable()</a> for CAT1D devices, <br />
 <a class="el" href="group__group__sysclk__imo__funcs.html#ga65e688803f1098d1d42ac635117104bc" title="Disables IMO. ">Cy_SysClk_ImoDisable()</a> for CAT1D devices, <br />
 <a class="el" href="group__group__sysclk__imo__funcs.html#gaff509bb102fcc7335d2a1c89a139e67a" title="Reports whether or not the selected IMO is enabled. ">Cy_SysClk_ImoIsEnabled()</a> for CAT1D devices, <br />
 <a class="el" href="group__group__sysclk__imo__funcs.html#ga8a32e62d8e2e086016de33b18bd87033" title="Enables the IMO during deepsleep mode. ">Cy_SysClk_ImoDeepsleepEnable()</a> for CAT1D devices, <br />
 <a class="el" href="group__group__sysclk__imo__funcs.html#ga2225594aadfb96b61f6c6d05ff02378b" title="Reports whether or not the selected IMO is enabled during deepsleep mode. ">Cy_SysClk_ImoIsDeepsleepEnabled()</a> for CAT1D devices, <br />
 <a class="el" href="group__group__sysclk__imo__funcs.html#gadd8190021e511b1c0b10db23b4e61c7d" title="Disables IMO during deepsleep mode. ">Cy_SysClk_ImoDeepsleepDisable()</a> for CAT1D devices, <br />
 <a class="el" href="group__group__sysclk__clk__fast__funcs.html#gae1f57c49981b7f62a3d09c040f000d29" title="Returns the Integer and Fractional clock divider for the fast clock. ">Cy_SysClk_ClkFastSrcGetDivider()</a> for CAT1C devices, <br />
 <a class="el" href="group__group__sysclk__clk__fast__funcs.html#ga2ce026196feb54b320018717643b35d8" title="Sets the clock divider for the fast clock, which sources the main processor. ">Cy_SysClk_ClkFastSrcSetDivider()</a> for CAT1C devices, <br />
 <a class="el" href="group__group__sysclk__clk__fast__funcs.html#gabe3c665ba505489d3c831daa44e4eabf" title="Reports the frequency of the fast clock. ">Cy_SysClk_ClkFastSrcGetFrequency()</a> for CAT1C devices,  </td><td>Bug fixes and new devices support.  </td></tr>
<tr>
<td rowspan="3">3.40 </td><td>Added CAT1C and CAT1D devices support.  </td><td>Support for new devices.  </td></tr>
<tr>
<td>New API's for PLL400M and PLL200M. </td><td>To handle the new PLL's for CAT1C devices.  </td></tr>
<tr>
<td><p class="starttd">New API's Added</p><ul>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#ga9e748343551cd15bfca189250e0af1c4" title="Configures 200M PLL. ">Cy_SysClk_Pll200MConfigure()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#gaaa6456259e31b786c7e161435b7dd450" title="Manually configures a 200M PLL based on user inputs. ">Cy_SysClk_Pll200MManualConfigure()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#ga030e569b07a163e58e84928773b9ad25" title="Reports configuration settings for 200M PLL. ">Cy_SysClk_Pll200MGetConfiguration()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#gaa755ea5198f4eebc6b7e7991bfe30c6e" title="Enables the 200M PLL. ">Cy_SysClk_Pll200MEnable()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#ga850229a9ff0d4af9d0f298f377ce5ba0" title="Reports whether or not the selected 200M PLL is enabled. ">Cy_SysClk_Pll200MIsEnabled()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#gaae48c98d74bbb34e049d2e8c17100685" title="Reports whether or not the selected 200M PLL is locked. ">Cy_SysClk_Pll200MLocked()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#ga40696a5667ca242332fb3de42b1b2994" title="Reports whether or not the selected 200M PLL lost its lock since the last time this function was call...">Cy_SysClk_Pll200MLostLock()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#ga8b42389042d11aaa84bd2e769f6b7b27" title="Disables the selected 200M PLL. ">Cy_SysClk_Pll200MDisable()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#gad498857f6d3c3b8df8dd176391d07f6f" title="Configures 400M PLL. ">Cy_SysClk_Pll400MConfigure()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#ga940fd6400c3ea9f37a0b26893ae8b42b" title="Manually configures a 400M PLL based on user inputs. ">Cy_SysClk_Pll400MManualConfigure()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#gad0d8b724b371f76ba51ed3378691d9df" title="Reports configuration settings for 400M PLL. ">Cy_SysClk_Pll400MGetConfiguration()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#gaa92e2b0dd3f211143fd66edf70fcd2ae" title="Enables the 400M PLL. ">Cy_SysClk_Pll400MEnable()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#ga156fecfbaecb9d502c74529f910fe24b" title="Reports whether or not the selected 400M PLL is enabled. ">Cy_SysClk_Pll400MIsEnabled()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#ga5455c05316aa399ef5afacf7648a3cf1" title="Reports whether or not the selected 400M PLL is locked. ">Cy_SysClk_Pll400MLocked()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#ga8e300a347373de8ab2c7d2ca89b05dee" title="Reports whether or not the selected 400M PLL lost its lock since the last time this function was call...">Cy_SysClk_Pll400MLostLock()</a></li>
<li><a class="el" href="group__group__sysclk__pll__funcs.html#ga8b42389042d11aaa84bd2e769f6b7b27" title="Disables the selected 200M PLL. ">Cy_SysClk_Pll200MDisable()</a></li>
<li><a class="el" href="group__group__sysclk__iho__funcs.html#gae014bbd531b0612fc784cdcf15784564" title="Enables the IHO during deepsleep mode. ">Cy_SysClk_IhoDeepsleepEnable()</a></li>
<li><a class="el" href="group__group__sysclk__iho__funcs.html#ga9de913cc5f378cba22fa53d77ab30b98" title="Reports whether or not the selected IHO is enabled during deepsleep mode. ">Cy_SysClk_IhoIsDeepsleepEnabled()</a></li>
<li><a class="el" href="group__group__sysclk__iho__funcs.html#ga43ed6359a710ce0581978ff5dfa4af19" title="Disables IHO during deepsleep mode. ">Cy_SysClk_IhoDeepsleepDisable()</a></li>
<li><a class="el" href="group__group__sysclk__ilo__funcs.html#ga37a81892a544b2278e039ca79f57b819" title="Enables the ILO. ">Cy_SysClk_IloSrcEnable()</a></li>
<li><a class="el" href="group__group__sysclk__ilo__funcs.html#gadc04fa9632d411a379cf36f182a916d4" title="Reports the Enabled/Disabled status of the ILO. ">Cy_SysClk_IloSrcIsEnabled()</a></li>
<li><a class="el" href="group__group__sysclk__ilo__funcs.html#ga9242347b2eec6b11cd614a75e05ad017" title="Disables the ILO. ">Cy_SysClk_IloSrcDisable()</a></li>
<li><a class="el" href="group__group__sysclk__ilo__funcs.html#gafd23ef6b241182bb67a5f26d6d3be167" title="Controls whether the ILO0 stays on during a hibernate, or through an XRES or brown-out detect (BOD) e...">Cy_SysClk_IloSrcHibernateOn()</a></li>
<li><a class="el" href="group__group__sysclk__pilo__funcs.html#ga6c21afebcb9f09b55c9589a682130e78" title="Enables the PILO as always on if Backup Domain is present. ">Cy_SysClk_PiloBackupEnable()</a></li>
<li><a class="el" href="group__group__sysclk__pilo__funcs.html#ga971789bdb0713f551f314eb405c6e2a1" title="Disables the PILO as always on if Backup Domain is present. ">Cy_SysClk_PiloBackupDisable()</a></li>
<li><a class="el" href="group__group__sysclk__pilo__funcs.html#ga9c3147eb364c04d6820a9089cf390044" title="Enables the PILO TCSC(Second order temperature curvature correction) Feature. ">Cy_SysClk_PiloTcscEnable()</a></li>
<li><a class="el" href="group__group__sysclk__pilo__funcs.html#gabf56d2b85a12e5e1dadc838619de6f08" title="Disables the PILO TCSC(Second order temperature curvature correction) Feature. ">Cy_SysClk_PiloTcscDisable()</a></li>
<li><a class="el" href="group__group__sysclk__alt__hf__funcs.html#gabc0dc28ac55e3606f2666742a8553962" title="Enables the ATLHF. ">Cy_SysClk_AltHfEnable()</a></li>
<li><a class="el" href="group__group__sysclk__alt__hf__funcs.html#gaaa7e7850d3f5674f78d51e99dd3a2d4a" title="Reports if ALTHF is enabled or not. ">Cy_SysClk_IsAltHfEnabled()</a></li>
<li><a class="el" href="group__group__sysclk__trim__funcs.html#ga853789a9e526c8735521be673bb4dbdc" title="Set ILO Trim Value. ">Cy_SysClk_IloSetTrim()</a></li>
<li><a class="el" href="group__group__sysclk__trim__funcs.html#gade35b7c0258b0eeabba38043134b1828" title="Gets the ILO Trim Value. ">Cy_SysClk_IloGetTrim()</a></li>
<li><a class="el" href="group__group__sysclk__mf__funcs.html#gaacb30352c5e747c40be8f15b673ee54a" title="Sets the source for the Medium frequency clock(clkMf). ">Cy_SysClk_ClkMfSetSource()</a></li>
<li><a class="el" href="group__group__sysclk__mf__funcs.html#ga336ac15ebc0e4d002717b0b15cd04bed" title="Reports the source for the Medium frequency clock (clkMf). ">Cy_SysClk_ClkMfGetSource()</a></li>
<li><a class="el" href="group__group__sysclk__clk__hf__funcs.html#gace8a5255f8579c17f4062dccb3ff3694" title="Enable/Disable the direct source selection as IMO for CLK_HF[[n]]. ">Cy_SysClk_ClkHfDirectSel()</a></li>
<li><a class="el" href="group__group__sysclk__clk__hf__funcs.html#ga58bb033cfac5881d026e32643ed6c6b7" title="Checks if direct source selection as IMO for CLK_HF[[n]] is enabled/disabled. ">Cy_SysClk_IsClkHfDirectSelEnabled()</a></li>
<li><a class="el" href="group__group__sysclk__clk__peripheral__group__funcs.html#ga99275f043f1a304bd579fc31783c2bd7" title="Gets the particular Slave Control value for a particular group. ">Cy_SysClk_PeriGroupGetSlaveCtl()</a></li>
<li><a class="el" href="group__group__sysclk__clk__peripheral__group__funcs.html#ga56bf76b1f4037514461e60a7428bf8a1" title="Gets the mask value of particular slave control register for a particular group. ">Cy_SysClk_IsPeriGroupSlaveCtlSet()</a></li>
<li><a class="el" href="group__group__sysclk__clk__peripheral__funcs.html#gaf121b7b35d0c907e84289c2f7b0106bf" title="Reports the frequency of the output of a given peripheral divider. ">Cy_SysClk_PeriPclkGetFrequency()</a></li>
<li><a class="el" href="group__group__sysclk__clk__peripheral__funcs.html#ga849645f956b39e9a1fc81822db691641" title="Reports the enabled/disabled state of the selected divider. ">Cy_SysClk_PeriPclkGetDividerEnabled()</a></li>
<li><a class="el" href="group__group__sysclk__clk__peripheral__funcs.html#gad2f14fb681ab88c7474c39c2d31f7fc8" title="Reports the corresponding CLK_HF* number for a particular PERI PCLK group. ">Cy_Sysclk_PeriPclkGetClkHfNum()</a></li>
<li><a class="el" href="group__group__sysclk__clk__mem__funcs.html#gaac472fea7c35a1108a2d587e2b32400d" title="Sets the clock divider for the Mem clock. ">Cy_SysClk_ClkMemSetDivider()</a></li>
<li><a class="el" href="group__group__sysclk__clk__mem__funcs.html#gaeb639022805581a220f2c91cfa76b85e" title="Reports the divider value for the Mem clock. ">Cy_SysClk_ClkMemGetDivider()</a></li>
<li><a class="el" href="group__group__sysclk__clk__mem__funcs.html#gad37e89c4cbafc9948f7e1f23ae922d04" title="Reports the frequency of the Mem clock. ">Cy_SysClk_ClkMemGetFrequency()</a></li>
</ul>
<p class="endtd"></p>
</td><td>New API's to handle CAT1B, CAT1C and CAT1D devices.  </td></tr>
<tr>
<td rowspan="3">3.30 </td><td>For PSoC64 device, allow CM0+ to call CY_PRA_FUNCTION_CALL_X_X API in functions accessing FUNCTION_POLICY registers. So that System Configuration structure is updated with new parameters.  </td><td>For PSoC64 device, System configuration can be done from CM0+ application.  </td></tr>
<tr>
<td>Fixed MISRA 2012 violations. </td><td>MISRA 2012 compliance.  </td></tr>
<tr>
<td>Return type doxygen updated for PSoC64 devices. </td><td>Doxygen update for PSoC64 devices.  </td></tr>
<tr>
<td>3.20 </td><td>Added new API's <a class="el" href="group__group__sysclk__fll__funcs.html#ga0e45b36747a2be6610f6fc9daefae02b">Cy_SysClk_FllGetFrequency</a> and <a class="el" href="group__group__sysclk__pll__funcs.html#ga219fd6d8d1d18090fe6d7002610ac021">Cy_SysClk_PllGetFrequency</a>. </td><td>Fetch the FLL and PLL frequency.  </td></tr>
<tr>
<td>3.10 </td><td>Support for CM33. </td><td>New devices support.  </td></tr>
<tr>
<td rowspan="2">3.0 </td><td>The behavior of <a class="el" href="group__group__sysclk__eco__funcs.html#gaadd2986e0b77ab0a714e4127ef1693f6">Cy_SysClk_EcoEnable</a> and <a class="el" href="group__group__sysclk__pll__funcs.html#ga5396ed00cc7ddeeb924bf00ee08311e5">Cy_SysClk_PllEnable</a> is changed - these functions disable the resource in case of enabling failure (timeout). </td><td>Usability enhancement.  </td></tr>
<tr>
<td>The implementation of <a class="el" href="group__group__sysclk__path__src__funcs.html#gab1c9f683f870696d41786c3df1eb331b">Cy_SysClk_ClkPathGetSource</a>, <a class="el" href="group__group__sysclk__fll__funcs.html#gad9d9c36d022475746375bddaba2b2065">Cy_SysClk_FllConfigure</a>, <a class="el" href="group__group__sysclk__fll__funcs.html#ga8e8ceae09a6a3e825c3ab9cea5561eed">Cy_SysClk_FllGetConfiguration</a>, <a class="el" href="group__group__sysclk__pll__funcs.html#gac5c498137bf7012e8e0f8b8e0dfba1f0">Cy_SysClk_PllConfigure</a> and <a class="el" href="group__group__sysclk__calclk__funcs.html#ga979f2ef437908618291bf3a935488412">Cy_SysClk_ClkMeasurementCountersGetFreq</a> is updated in accordance to the MISRA 2012 requirements. No behavioral changes. </td><td>MISRA 2012 compliance.  </td></tr>
<tr>
<td>2.20.1 </td><td>Updated source code comments. </td><td>Documentation update.  </td></tr>
<tr>
<td rowspan="3">2.20 </td><td><p class="starttd">Added the assertion mechanism to the following functions:</p><ul>
<li><a class="el" href="group__group__sysclk__eco__funcs.html#gab97a44bef89cdc85e5bcdc80098c1cef" title="Disables the external crystal oscillator (ECO). ">Cy_SysClk_EcoDisable()</a></li>
<li><a class="el" href="group__group__sysclk__ilo__funcs.html#gad07e09e072e4cd87baa319711d0549b5" title="Enables the ILO. ">Cy_SysClk_IloEnable()</a></li>
<li><a class="el" href="group__group__sysclk__ilo__funcs.html#gaece6af6547fbec8defb4defd1b10af1a" title="Controls whether the ILO stays on during a hibernate, or through an XRES or brown-out detect (BOD) ev...">Cy_SysClk_IloHibernateOn()</a></li>
<li><a class="el" href="group__group__sysclk__pilo__funcs.html#ga92e44b1390d7cabf2c597c45a5fdd309" title="Enables the PILO. ">Cy_SysClk_PiloEnable()</a></li>
<li><a class="el" href="group__group__sysclk__pilo__funcs.html#gaf73c2da9e8676f8b4cdfcd1f95e839f9" title="Disables the PILO. ">Cy_SysClk_PiloDisable()</a></li>
<li><a class="el" href="group__group__sysclk__wco__funcs.html#ga0990b94c499652b8f5c2dd1cf6abf95e" title="Disables the WCO. ">Cy_SysClk_WcoDisable()</a></li>
<li><a class="el" href="group__group__sysclk__wco__funcs.html#gaf254b104b1e1020545103779a573da17" title="Sets whether the WCO is bypassed or not. ">Cy_SysClk_WcoBypass()</a></li>
<li><a class="el" href="group__group__sysclk__clk__fast__funcs.html#ga05a3e0e120574d1205c2b2f9861dc733" title="Sets the clock divider for the fast clock, which sources the main processor. ">Cy_SysClk_ClkFastSetDivider()</a></li>
<li><a class="el" href="group__group__sysclk__clk__peri__funcs.html#ga872a11532b18a5438e9bea423fc4076f" title="Sets the clock divider for the peripheral clock tree. ">Cy_SysClk_ClkPeriSetDivider()</a></li>
<li><a class="el" href="group__group__sysclk__clk__lf__funcs.html#ga446424e5edb0121a1c6c06e7d87cd054" title="Sets the source for the low frequency clock(clkLf). ">Cy_SysClk_ClkLfSetSource()</a></li>
<li><a class="el" href="group__group__sysclk__clk__timer__funcs.html#ga4708822284fdca8103746e04e071f829" title="Sets the source for the timer clock (clk_timer). ">Cy_SysClk_ClkTimerSetSource()</a></li>
<li><a class="el" href="group__group__sysclk__clk__timer__funcs.html#ga47723df14931fa6403b7d3948dec3857" title="Sets the divider for the timer clock (clk_timer). ">Cy_SysClk_ClkTimerSetDivider()</a></li>
<li><a class="el" href="group__group__sysclk__clk__timer__funcs.html#ga3c024720aee53bd450eb68377a35bbf6" title="Enables the timer clock (clk_timer). ">Cy_SysClk_ClkTimerEnable()</a></li>
<li><a class="el" href="group__group__sysclk__clk__timer__funcs.html#gaa442df3e80e5c2dc763508731b155876" title="Disables the timer clock (clk_timer). ">Cy_SysClk_ClkTimerDisable()</a></li>
<li><a class="el" href="group__group__sysclk__clk__pump__funcs.html#ga14876f9c0e98b283defb6883fff0d906" title="Sets the source for the pump clock (clk_pump). ">Cy_SysClk_ClkPumpSetSource()</a></li>
<li><a class="el" href="group__group__sysclk__clk__pump__funcs.html#ga8d55fc79d235c3918ecb20b953afdb99" title="Sets the divider of the pump clock (clk_pump). ">Cy_SysClk_ClkPumpSetDivider()</a></li>
<li><a class="el" href="group__group__sysclk__clk__pump__funcs.html#ga0249934e0fd1d05a25f7565a8c5b6cde" title="Enables the pump clock (clk_pump). ">Cy_SysClk_ClkPumpEnable()</a></li>
<li><a class="el" href="group__group__sysclk__clk__pump__funcs.html#ga70d97ab2865f7705619ce7369baee81f" title="Disables the pump clock (clk_pump). ">Cy_SysClk_ClkPumpDisable()</a></li>
<li><a class="el" href="group__group__sysclk__clk__bak__funcs.html#gab72e0702bafe7df920708eacefdb40dd" title="Sets the source for the backup domain clock (clk_bak). ">Cy_SysClk_ClkBakSetSource()</a></li>
</ul>
<p class="endtd">Now, the functions described above halt in assertion when a PRA request returns not successful operation. This change is applicable only for the PSoC 64 family devices.  </p>
</td><td>Enhancements for the debugging process.  </td></tr>
<tr>
<td>Added <a class="el" href="group__group__sysclk__trim__funcs.html#ga8b6cd3386ea750d7bf7efd095bf0e978">Cy_SysClk_PiloInitialTrim</a> and <a class="el" href="group__group__sysclk__trim__funcs.html#ga2667f9d37c5c78d8a7f6c6e94c35e714">Cy_SysClk_PiloUpdateTrimStep</a> functions. Extended the <a class="el" href="group__group__sysclk__trim__funcs.html#ga6210a9bc87fc6e0159a6d2d790c789be">Cy_SysClk_PiloTrim</a> function to use the step-size value calculated for PILO based on the <a class="el" href="group__group__sysclk__trim__funcs.html#ga8b6cd3386ea750d7bf7efd095bf0e978">Cy_SysClk_PiloInitialTrim</a> and <a class="el" href="group__group__sysclk__trim__funcs.html#ga2667f9d37c5c78d8a7f6c6e94c35e714">Cy_SysClk_PiloUpdateTrimStep</a> functions call.   </td><td>User experience enhancement.  </td></tr>
<tr>
<td><ul>
<li>Added the warning that during a glitch-safe mux, the transition is not allowed to disable the previous clock source. See more info in the <a class="el" href="group__group__sysclk.html#group_sysclk_configuration">Configuration Considerations</a>.</li>
<li>Removed Known Issues table.  </li>
</ul>
</td><td>Documentation updates.  </td></tr>
<tr>
<td rowspan="3">2.10 </td><td>Updated SysClk functions for PSoC 64 devices. Now the SysClk functions can return PRA driver status value. </td><td>The SysClk driver uses the PRA driver to change the protected registers. A SysClk driver function that calls a PRA driver function will return the PRA error status code if the called PRA function returns an error. In these cases, refer to PRA return statuses. Refer to functions description for details.  </td></tr>
<tr>
<td>Updated the code of <a class="el" href="group__group__sysclk__path__src__funcs.html#ga54c618c89782d227fb8f292d1dc15625">Cy_SysClk_ClkPathGetFrequency</a> function. </td><td>Make the code more error-resistant to user errors for some corner cases.  </td></tr>
<tr>
<td>Minor documentation updates. </td><td>Documentation enhancement.  </td></tr>
<tr>
<td>2.0 </td><td>Updated the ECO trimming values calculation algorithm in the <a class="el" href="group__group__sysclk__eco__funcs.html#ga9d94ac55503404a0bdaf017fe33ecdbd">Cy_SysClk_EcoConfigure</a> implementation. <br />
 This change may invalidate the already used crystals, in cases: <br />
<ul>
<li>The crystal frequency is less than 16 MHz. <br />
</li>
<li>The maximum amplitude (internal calculation value) is less than 0.65 V. <br />
 For detail, refer the <a class="el" href="group__group__sysclk__eco__funcs.html#ga9d94ac55503404a0bdaf017fe33ecdbd">Cy_SysClk_EcoConfigure</a> documentation and the ECO Trimming section of the device TRM. </li>
</ul>
</td><td>Enhanced the ECO performance for high-noise conditions that result from simultaneous switching of GPIOs and/or high switching activity on the chip.  </td></tr>
<tr>
<td>1.60 </td><td>Added the following functions: <a class="el" href="group__group__sysclk__ext__funcs.html#ga164b8c0287b292af7bdab5e216831b9b">Cy_SysClk_ExtClkGetFrequency</a>, <a class="el" href="group__group__sysclk__eco__funcs.html#ga392db1f8d8504409017a3fedb95b8ee2">Cy_SysClk_EcoGetFrequency</a>,<br />
 <a class="el" href="group__group__sysclk__path__src__funcs.html#ga1256c8a7290cecf2b9553a1df582e797">Cy_SysClk_ClkPathMuxGetFrequency</a>, <a class="el" href="group__group__sysclk__path__src__funcs.html#ga54c618c89782d227fb8f292d1dc15625">Cy_SysClk_ClkPathGetFrequency</a>, <a class="el" href="group__group__sysclk__ilo__funcs.html#gae2af369242a12431544f998445a1e163">Cy_SysClk_IloIsEnabled</a>.<br />
 <a class="el" href="group__group__sysclk__pilo__funcs.html#gad1f5cd3318276616c1e0553f868142d2">Cy_SysClk_PiloIsEnabled</a>, <a class="el" href="group__group__sysclk__alt__hf__funcs.html#gaf948bdd0d4b0fbf2774642db55eea712">Cy_SysClk_AltHfGetFrequency</a>, <a class="el" href="group__group__sysclk__clk__hf__funcs.html#ga47252e1861afb4664f43c2e0a5e38055">Cy_SysClk_ClkHfIsEnabled</a>,<br />
 <a class="el" href="group__group__sysclk__clk__timer__funcs.html#ga34ffff27beaafa7a391f2aac5cf38bfd">Cy_SysClk_ClkTimerIsEnabled</a>, <a class="el" href="group__group__sysclk__clk__timer__funcs.html#gaa9fa2ca0beada63a72bdc86dae9e5896">Cy_SysClk_ClkTimerGetFrequency</a>, <a class="el" href="group__group__sysclk__clk__pump__funcs.html#gacd99d1c6e448c715e50e99462b6fe923">Cy_SysClk_ClkPumpIsEnabled</a> and<br />
 <a class="el" href="group__group__sysclk__clk__pump__funcs.html#ga3115e52203b8ac7c74a0bedc0083b925">Cy_SysClk_ClkPumpGetFrequency</a>. </td><td>API enhancement.  </td></tr>
<tr>
<td>1.50 </td><td><a class="el" href="group__group__sysclk__clk__hf__funcs.html#gafa8c21271b8cb1b1fd9f7fb489a8d2b3">Cy_SysClk_ClkHfGetFrequency</a> is updated to reuse the <a class="el" href="group__group__system__config__globals.html#gad6c61e43c7d81802c759a8f0046bdc12">cy_BleEcoClockFreqHz</a> global system variable. </td><td>API enhancement.  </td></tr>
<tr>
<td>1.40.2 </td><td>Update documentation based on collateral review feedback. </td><td>User experience enhancement.  </td></tr>
<tr>
<td>1.40.1 </td><td>Fix compiler warning. </td><td></td></tr>
<tr>
<td rowspan="4">1.40 </td><td>Updated the following functions implementation: <a class="el" href="group__group__sysclk__pll__funcs.html#gac5c498137bf7012e8e0f8b8e0dfba1f0">Cy_SysClk_PllConfigure</a> and <a class="el" href="group__group__sysclk__pll__funcs.html#ga5396ed00cc7ddeeb924bf00ee08311e5">Cy_SysClk_PllEnable</a>. </td><td>Fixed the <a class="el" href="group__group__sysclk__pll__funcs.html#gac5c498137bf7012e8e0f8b8e0dfba1f0">Cy_SysClk_PllConfigure</a> API function behaviour when it is called with a bypass mode, <br />
 Fixed the <a class="el" href="group__group__sysclk__pll__funcs.html#ga5396ed00cc7ddeeb924bf00ee08311e5">Cy_SysClk_PllEnable</a> API function behaviour when it is called with a zero timeout.   </td></tr>
<tr>
<td>Added the following functions: <a class="el" href="group__group__sysclk__mf__funcs.html#ga283d5413436f7a9f05b24d52ac2026be">Cy_SysClk_MfoEnable</a>, <a class="el" href="group__group__sysclk__mf__funcs.html#ga1dd74d05d2b8b2d0b5ef588a304c2a66">Cy_SysClk_MfoIsEnabled</a>,<br />
 <a class="el" href="group__group__sysclk__mf__funcs.html#gaf8ca8fc33fc99fd7c7af45048ff3e17e">Cy_SysClk_MfoDisable</a>, <a class="el" href="group__group__sysclk__mf__funcs.html#ga195a613b088f27c5d7667a6fecb0bbbc">Cy_SysClk_ClkMfEnable</a>, <a class="el" href="group__group__sysclk__mf__funcs.html#gab27fbf5f4e7b9856014fbf7c59eff78b">Cy_SysClk_ClkMfIsEnabled</a>,<br />
 <a class="el" href="group__group__sysclk__mf__funcs.html#ga8cc7f7635c71f5ea4da74950bc6521a4">Cy_SysClk_ClkMfDisable</a>, <a class="el" href="group__group__sysclk__mf__funcs.html#ga420525301a89c8f5f45c97a0fb37ea6f">Cy_SysClk_ClkMfGetDivider</a>, <a class="el" href="group__group__sysclk__mf__funcs.html#ga54c1e75dcdea293cdfd2662ceffa26e0">Cy_SysClk_ClkMfSetDivider</a>,<br />
. <a class="el" href="group__group__sysclk__mf__funcs.html#gaf917222c5e1a0bb3dc2f7d398dcff05c">Cy_SysClk_ClkMfGetFrequency</a> </td><td>New device support.  </td></tr>
<tr>
<td>Added the following new API functions <a class="el" href="group__group__sysclk__fll__funcs.html#gab266867b8e4f71d58467c33c53f6f0e2">Cy_SysClk_FllIsEnabled</a>, <a class="el" href="group__group__sysclk__pll__funcs.html#gae3ee5e192525df92ea07b32a3eb3d295">Cy_SysClk_PllIsEnabled</a>,<br />
 <a class="el" href="group__group__sysclk__ext__funcs.html#gad4b77c61d47878007b5c50e3baf13e51">Cy_SysClk_ExtClkSetFrequency</a>, <a class="el" href="group__group__sysclk__clk__hf__funcs.html#gafa8c21271b8cb1b1fd9f7fb489a8d2b3">Cy_SysClk_ClkHfGetFrequency</a>, <a class="el" href="group__group__sysclk__clk__fast__funcs.html#ga2fd7d9e080181356a1e6a5a72d948119">Cy_SysClk_ClkFastGetFrequency</a>,<br />
 <a class="el" href="group__group__sysclk__clk__peri__funcs.html#ga8db0b9f751e98d8b19054e0879f965c4">Cy_SysClk_ClkPeriGetFrequency</a> and <a class="el" href="group__group__sysclk__clk__slow__funcs.html#ga7ca0c247dee5e69b25f173240db9ed53">Cy_SysClk_ClkSlowGetFrequency</a> </td><td>Enhancement based on usability feedback  </td></tr>
<tr>
<td>Deprecated the following macros: CY_SYSCLK_DIV_ROUND and CY_SYSCLK_DIV_ROUNDUP </td><td>Macros were moved into <a class="el" href="group__group__syslib.html">SysLib (System Library)</a>  </td></tr>
<tr>
<td rowspan="2">1.30 </td><td>Updated the following functions implementation: <a class="el" href="group__group__sysclk__eco__funcs.html#ga9d94ac55503404a0bdaf017fe33ecdbd">Cy_SysClk_EcoConfigure</a> and <a class="el" href="group__group__sysclk__fll__funcs.html#gad9d9c36d022475746375bddaba2b2065">Cy_SysClk_FllConfigure</a>. </td><td>Math library dependency is removed, the floating-point math is replaced with integer math.  </td></tr>
<tr>
<td>Updated the following functions implementation: <a class="el" href="group__group__sysclk__eco__funcs.html#gaadd2986e0b77ab0a714e4127ef1693f6">Cy_SysClk_EcoEnable</a>, <a class="el" href="group__group__sysclk__eco__funcs.html#ga55bbf5f409d57259aff005b29be026e0">Cy_SysClk_EcoGetStatus</a>, <a class="el" href="group__group__sysclk__fll__funcs.html#ga8e8ceae09a6a3e825c3ab9cea5561eed">Cy_SysClk_FllGetConfiguration</a> <br />
 and <a class="el" href="group__group__sysclk__pm__funcs.html#ga34bd0e837cdf7d0953a7e0f5219905b5">Cy_SysClk_DeepSleepCallback</a>. <br />
 The <a class="el" href="group__group__sysclk__pm__funcs.html#ga34bd0e837cdf7d0953a7e0f5219905b5">Cy_SysClk_DeepSleepCallback</a> now implements all four SysPm callback modes <a class="el" href="group__group__syspm__data__enumerates.html#gae06cd8869fe61d709ad6145ca9f3cd63">cy_en_syspm_callback_mode_t</a>. <br />
 The actions that were done in <a class="el" href="group__group__syspm__data__enumerates.html#ggae06cd8869fe61d709ad6145ca9f3cd63ab7ec706d80b347433d0063f2a8115784">CY_SYSPM_CHECK_READY</a> case are moved to <a class="el" href="group__group__syspm__data__enumerates.html#ggae06cd8869fe61d709ad6145ca9f3cd63a7d302375276b3b5f250a8208c999b558">CY_SYSPM_BEFORE_TRANSITION</a>. <br />
 So the <a class="el" href="structcy__stc__syspm__callback__t.html#a1b49c2454ac29e52261e28eb9071413b">cy_stc_syspm_callback_t::skipMode</a> must be set to 0UL. </td><td>Defect fixing.  </td></tr>
<tr>
<td rowspan="4">1.20 </td><td>Flattened the organization of the driver source code into the single source directory and the single include directory.  </td><td>Driver library directory-structure simplification.  </td></tr>
<tr>
<td>Updated <a class="el" href="group__group__sysclk__fll__funcs.html#ga3227d4ab9e531127a7cc7bd27c49a499">Cy_SysClk_FllLocked</a> function description </td><td>The SRSS_ver1 HW details clarification  </td></tr>
<tr>
<td>Removed the following functions:<ul>
<li>Cy_SysClk_FllLostLock</li>
<li>Cy_SysClk_WcoConfigureCsv</li>
<li>Cy_SysClk_ClkHfConfigureCsv  </li>
</ul>
</td><td>No hardware support for the removed functions.  </td></tr>
<tr>
<td>Added register access layer. Use register access macros instead of direct register access using dereferenced pointers. </td><td>Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number.  </td></tr>
<tr>
<td>1.11 </td><td><p class="starttd">Updated the following functions. Now they use a semaphore when try to read the status or configure the SysClk measurement counters:</p><ul>
<li><a class="el" href="group__group__sysclk__calclk__funcs.html#ga0a87e123411d5711344780ddfa492f37" title="Assigns clocks to the clock measurement counters, and starts counting. ">Cy_SysClk_StartClkMeasurementCounters()</a></li>
<li><a class="el" href="group__group__sysclk__calclk__funcs.html#ga979f2ef437908618291bf3a935488412" title="Calculates the frequency of the indicated measured clock (clock1 or clock2). ">Cy_SysClk_ClkMeasurementCountersGetFreq()</a></li>
</ul>
<p class="endtd">Now <a class="el" href="group__group__sysclk__calclk__funcs.html#ga979f2ef437908618291bf3a935488412" title="Calculates the frequency of the indicated measured clock (clock1 or clock2). ">Cy_SysClk_ClkMeasurementCountersGetFreq()</a> returns zero value, if during measurement device was in the Deep Sleep or partially blocking flash operation occurred  </p>
</td><td>Added arbiter mechanism for correct usage of the SysClk measurement counters  </td></tr>
<tr>
<td>1.10.1 </td><td>Renamed Power Management section to Low Power Callback section </td><td>Documentation update and clarification  </td></tr>
<tr>
<td rowspan="5">1.10 </td><td>Updated FLL parameter calculation </td><td>Support low frequency sources  </td></tr>
<tr>
<td>Added <a class="el" href="group__group__sysclk__pilo__funcs.html#gad609f2077dfc69a271fb94cba111ad42" title="Sets the PILO trim bits, which adjusts the PILO frequency. ">Cy_SysClk_PiloSetTrim()</a> and Cy_SysclkPiloGetTrim() functions </td><td>Support PILO manual trims  </td></tr>
<tr>
<td>Made Cy_SysClk_FllLostLock() function dependent on SRSS v1 </td><td>Feature is not supported in SRSS v1  </td></tr>
<tr>
<td>Updated <a class="el" href="group__group__sysclk__pm__funcs.html#ga34bd0e837cdf7d0953a7e0f5219905b5" title="Callback function to be used when entering system Deep Sleep mode. ">Cy_SysClk_DeepSleepCallback()</a> to save/restore both FLL and PLL settings </td><td>The function should return when the lock is established or a timeout has occurred  </td></tr>
<tr>
<td>General documentation updates </td><td></td></tr>
<tr>
<td>1.0 </td><td>Initial version </td><td></td></tr>
</table>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a>
API Reference</h2></td></tr>
<tr class="memitem:group__group__sysclk__macros"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html">Macros</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__enums"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__enums.html">General Enumerated Types</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__ext"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__ext.html">External Clock Source (EXTCLK)</a></td></tr>
<tr class="memdesc:group__group__sysclk__ext"><td class="mdescLeft">&#160;</td><td class="mdescRight">The External Clock Source (EXTCLK) is a clock source routed into SOC through a GPIO pin. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__eco"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__eco.html">External Crystal Oscillator (ECO)</a></td></tr>
<tr class="memdesc:group__group__sysclk__eco"><td class="mdescLeft">&#160;</td><td class="mdescRight">The External Crystal Oscillator (ECO) is a clock source that consists of an oscillator circuit that drives an external crystal through its dedicated ECO pins. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__path__src"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__path__src.html">Clock Path Source</a></td></tr>
<tr class="memdesc:group__group__sysclk__path__src"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock paths are a series of multiplexers that allow a source clock to drive multiple clocking resources down the chain. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__fll"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__fll.html">Frequency Locked Loop (FLL)</a></td></tr>
<tr class="memdesc:group__group__sysclk__fll"><td class="mdescLeft">&#160;</td><td class="mdescRight">The FLL is a clock generation circuit that can be used to produce a higher frequency clock from a reference clock. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__pll"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__pll.html">Phase Locked Loop (PLL)</a></td></tr>
<tr class="memdesc:group__group__sysclk__pll"><td class="mdescLeft">&#160;</td><td class="mdescRight">The PLL is a clock generation circuit that can be used to produce a higher frequency clock from a reference clock. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__ilo"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__ilo.html">Internal Low-Speed Oscillator (ILO)</a></td></tr>
<tr class="memdesc:group__group__sysclk__ilo"><td class="mdescLeft">&#160;</td><td class="mdescRight">The ILO operates with no external components and outputs a stable clock at 32.768 kHz nominal. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__pilo"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__pilo.html">Precision Internal Low-Speed Oscillator (PILO)</a></td></tr>
<tr class="memdesc:group__group__sysclk__pilo"><td class="mdescLeft">&#160;</td><td class="mdescRight">PILO provides a higher accuracy 32.768 kHz clock than the <a class="el" href="group__group__sysclk__ilo.html">ILO</a>. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__calclk"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__calclk.html">Clock Measurement</a></td></tr>
<tr class="memdesc:group__group__sysclk__calclk"><td class="mdescLeft">&#160;</td><td class="mdescRight">These functions measure the frequency of a specified clock relative to a reference clock. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__trim"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__trim.html">Clock Trim (ILO, PILO)</a></td></tr>
<tr class="memdesc:group__group__sysclk__trim"><td class="mdescLeft">&#160;</td><td class="mdescRight">These functions perform a single trim operation on the ILO or PILO. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__pm"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__pm.html">Low Power Callback</a></td></tr>
<tr class="memdesc:group__group__sysclk__pm"><td class="mdescLeft">&#160;</td><td class="mdescRight">Entering and exiting low power modes require compatible clock configurations to be set before entering low power and restored upon wake-up and exit. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__wco"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__wco.html">Watch Crystal Oscillator (WCO)</a></td></tr>
<tr class="memdesc:group__group__sysclk__wco"><td class="mdescLeft">&#160;</td><td class="mdescRight">The WCO is a highly accurate 32.768 kHz clock source capable of operating in all power modes (excluding the Off mode). <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__lpeco"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__lpeco.html">Low-Power External Crystal Oscillator (LPECO)</a></td></tr>
<tr class="memdesc:group__group__sysclk__lpeco"><td class="mdescLeft">&#160;</td><td class="mdescRight">The LPECO provides high-frequency clocking using an external crystal connected to the LPECO_IN and LPECO_OUT pins. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__hf"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__hf.html">High-Frequency Clocks</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__hf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multiple high frequency clocks (CLK_HF) are available in the device. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__fast"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__fast.html">Fast Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__fast"><td class="mdescLeft">&#160;</td><td class="mdescRight">The fast clock drives the "fast" processor (e.g. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__peri"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__peri.html">Peripheral Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__peri"><td class="mdescLeft">&#160;</td><td class="mdescRight">The peripheral clock is a divided clock of CLK_HF0 (<a class="el" href="group__group__sysclk__clk__hf.html">HF Clocks</a>). <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__peripheral"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__peripheral.html">Peripherals Clock Dividers</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__peripheral"><td class="mdescLeft">&#160;</td><td class="mdescRight">There are multiple peripheral clock dividers that, in effect, create multiple separate peripheral clocks. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__peripheral__group"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__peripheral__group.html">Peripheral Group(MMIO Group) Controls</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__peripheral__group"><td class="mdescLeft">&#160;</td><td class="mdescRight">All the peripherals in the SOC belongs to certain MMIO groups. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__slow"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__slow.html">Slow Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__slow"><td class="mdescLeft">&#160;</td><td class="mdescRight">The slow clock is the source clock for the "slow" processor (e.g. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__alt__hf"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__alt__hf.html">Alternative High-Frequency Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__alt__hf"><td class="mdescLeft">&#160;</td><td class="mdescRight">In the BLE-enabled PSoC6 devices, the <a class="el" href="group__group__ble__clk.html">BLE ECO (Bluetooth&reg; LE ECO Clock)</a> clock is connected to the system Alternative High-Frequency Clock input. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__lf"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__lf.html">Low-Frequency Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__lf"><td class="mdescLeft">&#160;</td><td class="mdescRight">The low-frequency clock is the source clock for the <a class="el" href="group__group__mcwdt.html">MCWDT (Multi-Counter Watchdog)</a> and can be the source clock for <a class="el" href="group__group__sysclk__clk__bak.html">Backup Domain Clock</a>, which drives the <a class="el" href="group__group__rtc.html">RTC (Real-Time Clock)</a>. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__timer"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__timer.html">Timer Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__timer"><td class="mdescLeft">&#160;</td><td class="mdescRight">The timer clock can be a source for the alternative clock driving the <a class="el" href="group__group__arm__system__timer.html">SysTick (Arm&reg; System Timer)</a>. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__pump"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__pump.html">Pump Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__pump"><td class="mdescLeft">&#160;</td><td class="mdescRight">The pump clock is a clock source used to provide analog precision in low voltage applications. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__bak"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__bak.html">Backup Domain Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__bak"><td class="mdescLeft">&#160;</td><td class="mdescRight">The backup domain clock drives the <a class="el" href="group__group__rtc.html">RTC (Real-Time Clock)</a>. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__mf"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__mf.html">Medium Frequency Domain Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__mf"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Medium Frequency Domain Clock is present only in SRSS_ver1_3. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__iho"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__iho.html">Internal High Frequency(IHO) Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__iho"><td class="mdescLeft">&#160;</td><td class="mdescRight">The IHO Clock is Internal High-speed Oscillator, which is present in CAT1B(48MHz) and CAT1D(50MHz) devices. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__imo"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__imo.html">Internal Main Oscillator(IMO) Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__imo"><td class="mdescLeft">&#160;</td><td class="mdescRight">The IMO Clock is Internal Main Oscillator, which is present in CAT1A/CAT1B/CAT1C and CAT1D devices, where as it is it is 8MHz in CAT1A/CAT1B/CAT1C, and CAT1D supports two instances of IMO i.e. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__mem"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__mem.html">Mem Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__mem"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock for the Memories. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__pwr"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__pwr.html">Power Clock</a></td></tr>
<tr class="memdesc:group__group__sysclk__clk__pwr"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock for the power architecture components. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__sysclk__clk__ref__enums"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__ref__enums.html">Group_sysclk_clk_ref_enums</a></td></tr>
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<tr class="memitem:group__group__sysclk__clk__ref__structs"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__ref__structs.html">Group_sysclk_clk_ref_structs</a></td></tr>
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<tr class="memitem:group__group__sysclk__clk__ilo__enums"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__ilo__enums.html">Group_sysclk_clk_ilo_enums</a></td></tr>
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